1. Field of the Invention
The present invention generally relates to fuses within semiconductor devices and more particularly to an improved method of forming a structure having a cavity around a gate stack conductor fuse.
2. Description of the Related Art
Semiconductor integrated circuits (IC) and their manufacturing techniques are well known. In a typical integrated circuit, a large number of semiconductor devices may be fabricated on a silicon substrate. To achieve the desired functionality, a plurality of conductors are typically provided to couple selected devices together. In some integrated circuits, conductive links are coupled to fuses, which may be cut or blown after fabrication using lasers or excessive current/voltage.
In a dynamic random access memory (DRAM) circuit, for example, fuses may be employed during manufacturing to protect some of the transistors' gate stacks from destruction due to inadvertent built-up of charges. Once fabrication of the IC is substantially complete, the fuses may be blown or cut to permit the DRAM circuit to function as if the protective current paths never existed.
Fusible links generally comprise metal lines that can be explosively fused open by application of excessive energy which causes a portion of the link material to vaporize and a portion to melt. Typically, the fusible link is thin and is made of aluminum or polysilicon. Alternatively, the fuse link may be made of the same metals as the chip conductors.
The increasing speed requirements of logic chips are the driving force behind these fusible link materials. More commonly, fuses may be employed to set the enable bit and the address bits of a redundant array element in a DRAM circuit.
FIG. 1 illustrates a typical dynamic random access memory integrated circuit, having a main memory array 102. To facilitate replacement of a defective main array element within the main memory array 102, a redundant array 104 is provided as shown. A plurality of fuses in a fuse array 106 are coupled to redundant array 104 via a fuse latch array 108 and a fuse decoder circuit 110. To replace a defective main memory array element, individual fuses in the fuse array 106 may be blown or cut to set their values to either a "1" or a "0" as required by the decoder circuit.
During operation, the values of the fuses in the fuse array 106 are typically loaded into a fuse latch array 108 upon power up. These values are then decoded by fuse decoder circuit 110 during run time, thereby facilitating the replacement of specific failed main memory array elements with specific redundant elements of redundant array 104. Techniques for replacing failed main memory array elements with redundant array elements are well known in the art and will not be discussed in great detail herein.
As mentioned above, the fuse links within the fuse array 106 may be selectively blown or cut with a laser beam or excess current/voltage. Once blown the fuse changes from a highly conductive state to a highly resistive (i.e., non-conductive) state. A blown fuse inhibits current from flowing through and represents an open circuit to the current path. With reference to FIG. 2A, fuse links 202, 204, 206, and 208 of the fuse array element 106 are shown in their unblown (i.e., conductive) state. In FIG. 2B, fuse link 204 has been blown ("opened"), thereby inhibiting the flow of current therethrough.
However, if the fuse link material is not sufficiently dispersed within the surrounding area, the fuse link may still represents a conductive path even after it is theoretically blown. In other words, especially with electrically blown fuses, the fuse blow is sometimes unreliable. Therefore, cavities or areas of adsorption material are often placed adjacent the fuse link material to provide a location for the melted and vaporized material to disburse.